SN74LS (ACTIVE) Quad 2-input exclusive-NOR gates with open collector outputs. Datasheet ( KB). Description click to collapse contents. The ‘LS is . services. Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is accompanied by all. Symbol VCC TA VOH IOL Supply Voltage Operating Ambient Temperature Range Output Voltage High Output Current Low Parameter Min Typ Max Unit.

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If one but not both inputs are high 1a low output 0 results. Both include four independent, two-input, XNOR gates.

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From Wikipedia, the free encyclopedia. For the NOR constructions, the upper arrangement requires fewer gates. This article dataasheet additional citations for verification. By using this site, you agree to the Terms of Use and Privacy Policy. Unsourced material may be challenged and removed.

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It does not implement a logical “equivalence” function, unlike two-input Exclusive OR gates; for example its output is L ow when all inputs are L ow. Views Read Edit View history.

The two-input version implements logical equalitybehaving according to the truth table to the right, and hence the gate is sometimes called an “equivalence gate”. December Learn how and when to remove this template message. This page was last edited on 24 Octoberat There are two symbols for XNOR gates: For the NOR constructions, the upper arrangement requires fewer gates.

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In other projects Wikimedia Commons. A high output 1 results if both of the inputs to the gate are the same. There are two symbols for XNOR gates: A high output 1 results if both of the inputs to the gate are the same. XNOR gate circuit using three mixed gates. XNOR gate circuit using three mixed gates. For the NAND constructions, the lower arrangement offers the advantage 742666 a shorter propagation delay the time delay datasbeet an input changing and the output changing.

The two-input version implements logical equalitydatasheett according to the truth table to the right, and hence the gate is sometimes called an “equivalence gate”. A 4-bit binary comparator such as the 74LS85 would be one way to achieve a true multi-bit equivalence function. Retrieved 6 May If one but not both inputs are high 1a low output 0 results. Please help improve this article by adding citations to reliable sources.

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December Learn how and when to remove this template message. This page was last dtasheet on 24 Octoberat Datasheets are readily available in most datasheet databases and suppliers.

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Unsourced material may be challenged and removed. This article needs additional citations for verification. It does not implement a logical “equivalence” function, unlike two-input Exclusive OR gates; for example its output is L ow datashee all inputs are L ow. Views Read Edit View history.

Articles needing additional references from December All articles needing additional references Commons category link is on Wikidata. Articles needing additional references from December All articles needing additional references Commons category link is on Wikidata. Retrieved 6 May For the NAND constructions, the lower arrangement offers the advantage of a shorter propagation delay the time delay between an input changing and the output changing.

However, extending the concept of the binary logical operation to three inputs, the SN74S with two shared “C” and four independent “A” and “B” inputs for its four outputs, was a device that followed the truth table:. Both include four independent, two-input, XNOR gates. However, extending the concept of the binary logical operation to three inputs, the SN74S with two shared “C” and four independent “A” and “B” inputs for its four outputs, was a device that followed the truth table:.